This invention relates in general to FIFO memory devices and in particular to a system for notifying a microprocessor and a direct memory access controller (DMA) or a co-processor of impending FIFO overruns and underruns so as to prevent these events from occurring.
Peripheral devices such as serializers and disk data controllers used in microprocessor-based systems usually include a FIFO for storing data. When the FIFO is used to store data received from a source outside the system (receive FIFO) so that the data stored may be read into a main memory by a DMA, sometimes FIFO overrun occurs in which the data transferred to the FIFO from the external source exceeds its capacity so that some of the data will be lost. In such event, it is important to detect a condition where impending FIFO overrun is going to occur in order to read some of the stored data into the main memory to make more room for data from the external source. If data is being transmitted from the FIFO to an external source (transmit FIFO) a FIFO underrun can occur where the FIFO runs out of data in which case garbage will be transmitted. In such event, it is desirable to detect the condition of impending FIFO underrun in order to read more data into the FIFO from the main memory.
In conventional devices, a receive or transmit FIFO will provide one notification level. This level is the number of filled (receive FIFO) or empty (transmit FIFO) sites in the FIFO which is the "safe" number before a signal must be sent requiring action from the DMA or the central processing unit in the microprocessor-based system. The conventional peripheral device will initiate either a transfer request to the DMA, or an interrupt request to the central processing unit (CPU) when the filled (receive FIFO) or empty (transmit FIFO) sites in the FIFO exceeds the "safe" number. If the user chooses to send an interrupt request to the CPU, time-wasting intervention by the CPU is required. If the user chooses to initiate a transfer request to the DMA, while CPU intervention is avoided, the DMA may not be able to obtain the bus immediately. If this happens in the case of the receive FIFO, data will continue to arrive at the receive FIFO when the DMA is unable to transfer data out from the FIFO through the bus. A FIFO overrun will occur resulting in lost data. For a transmit FIFO, when the DMA is unable to obtain the bus immediately, the transmit FIFO will continue to transfer data out when the DMA is unable to feed any data into the FIFO. In this situation a FIFO underrun will occur and garbage will be transmitted until the DMA obtains control of the bus. When FIFO overruns or underruns occur, the data transmission process to or from the external source will have to be repeated to assure data accuracy.
Thus, in conventional systems, the user must choose between time-wasting CPU intervention and running the risk of having to repeat data transmissions when FIFO underruns and overruns do occur. One example of a peripheral employing a conventional system for providing notification of impending FIFO overruns and underruns is the DP8466A disk data controller from National Semi-Conductor Corporation of Santa Clara, Calif. It is therefore desirable to provide an improved system for providing notification of impending FIFO overruns and underruns.